1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same and, more particularly, to a semiconductor device having a MOS (Metal-Oxide-Semiconductor) nonvolatile memory cell with a floating gate electrode, and a MOS field effect transistor (to be referred to as a MOS transistor hereinafter), and a method of manufacturing the same.
2. Description of the Prior Art
In general, a semiconductor device incorporating a nonvolatile memory and a logic circuit (e.g., circuit having a nonvolatile memory control function) on one chip comprises, on a semiconductor substrate, a MOS nonvolatile memory cell (to be simply referred to as a memory cell hereinafter) with a multilayered gate structure of floating and control gate electrodes, and a MOS transistor operating as a logic circuit element.
FIGS. 1A to 1F show an example of a method of manufacturing a conventional semiconductor device having a nonvolatile memory cell and a MOS transistor.
As shown in FIG. 1A, silicon oxide element isolation regions 102 are formed in the surface region of a silicon substrate 101. The element isolation regions 102 demarcate many active regions in the surface region of the silicon substrate 101 in both a memory cell region A101 where memory cells are going to be formed and a logic circuit region A102 where MOS transistors are going to be formed. For descriptive convenience, single active regions are formed in the memory cell and logic circuit regions A101 and A102, respectively.
A silicon oxide film (not shown) is formed on the entire surface of the silicon substrate 101, and a doped polysilicon film (not shown) is deposited on the silicon oxide film. The silicon oxide film and the polysilicon film are simultaneously patterned into a predetermined shape to form a tunnel insulating film 103 and a floating gate electrode 104 in the memory cell region A101 on the silicon substrate 101.
As shown in FIG. 1B, a silicon oxide film and a doped polysilicon film (neither is shown) are sequentially deposited to cover the entire silicon substrate 101, and patterned into the same shape as the floating gate electrode 104, thereby forming an internal insulating film 105 and a control gate electrode 106 on the floating gate electrode 104. At this time, a deposited silicon oxide film 107 and a polysilicon film 108 remain in the logic circuit region A102 on the silicon substrate 101.
As shown in FIG. 1C, the silicon oxide film 107 and the polysilicon film 108 are simultaneously patterned into a predetermined shape to form a gate insulating film 109 and a gate electrode 110 in the logic circuit region A102.
As shown in FIG. 1D, a silicon oxide film (not shown) is deposited to cover the entire silicon substrate 101, and then etched back to form a pair of silicon oxide sidewall spacers 112A on the sides of the floating and control gate electrodes 104 and 106, and a pair of silicon oxide sidewall spacers 112B on the sides of the gate electrode 110.
Subsequently, impurity ions are implanted into the surface region of the silicon substrate 101 using the control gate electrode 106, gate electrode 110, and sidewall spacers 112A and 112B as a mask. This ion implantation forms a pair of source and drain regions 111A in the memory cell region A101, and a pair of source and drain regions 111B in the logic circuit region A102.
As a result, a MOS memory cell 121 made up of the pair of source and drain regions 11A, tunnel insulating film 103, floating gate electrode 104, internal insulating film 105, and control gate electrode 106 is formed in the memory cell region A101. A MOS transistor 122 made up of the pair of source and drain regions 111B, gate insulating film 109, and gate electrode 110 is formed in the logic circuit region A102.
As shown in FIG. 1E, silicon oxide is deposited to cover the entire silicon substrate 101, thereby forming an interlevel insulating film 113. Then, the surface of the interlevel insulating film 113 is planarized. The interlevel insulating film 113 is selectively etched using a patterned photoresist film as a mask, thereby forming contact holes 114 and 115 extending through the interlevel insulating film 113. The bottoms of the contact holes 114 and 115 reach the control gate electrode 106 and one source/drain region 111B, respectively.
As shown in FIG. 1F, a tungsten film (not shown) is deposited on the interlevel insulating film 113 to a thickness enough to completely fill the internal spaces of the contact holes 114 and 115. This tungsten film is patterned into a predetermined shape, thereby forming interconnection layers 116 and 117.
In this manner, a conventional semiconductor device in which the memory cell 121 and the MOS transistor 122 are formed on the silicon substrate 101 is completed.
In the conventional semiconductor device manufacturing method shown in FIGS. 1A to 1F, the control gate electrode 106 of the memory cell 121 and the gate electrode 110 of the MOS transistor 122 are formed by patterning identical polysilicon films. However, patterning the polysilicon film is separately performed for the control gate electrode 106 and the gate electrode 110. The polysilicon films cannot be patterned at once because the memory cell 121 and the MOS transistor 122 are different in design rule. That is, the MOS transistor 122 has a finer structure than the memory cell 121. Since the memory cell 121 has the multilayered gate structure of the floating and control gate electrodes 104 and 106, the gate electrode 110 cannot be formed prior to formation of the floating gate electrode 104. For this reason, the manufacturing process concerning formation of the MOS transistor 122 must be greatly changed, which makes it difficult to share the manufacturing process and the manufacturing equipment. Hence, the manufacturing cost increases.
When the memory cell 121 is micropatterned for high integration degree, the planar shapes of the control and floating gate electrodes 106 and 104 are downsized. Accordingly, the overlapping area between the control and floating gate electrodes 106 and 104 decreases to decrease the electrostatic capacitance. A small electrostatic capacitance between the control and floating gate electrodes 106 and 104 decreases the capacitive coupling ratio (ratio of the electrostatic capacitance between the control and floating gate electrodes 106 and 104 to that between the floating gate electrode 104 and the silicon substrate 101). This makes it difficult to transfer a voltage applied to the control gate electrode 106 to a channel region formed between the pair of source and drain regions 11A. This increases the driving voltage.
The present invention has been made in consideration of the above situation, and has as its first object to provide a semiconductor device in which the manufacturing process and the manufacturing equipment can be easily shared to reduce the manufacturing cost, and a method of manufacturing the same.
It is the second object of the present invention to provide a semiconductor device capable of forming a nonvolatile memory cell without greatly changing the manufacturing process concerning a field effect transistor, and a method of manufacturing the same.
It is the third object of the present invention to provide a semiconductor device capable of incorporating a nonvolatile memory cell that can be driven by a low voltage, and a method of manufacturing the same.
To achieve the first and second objects, according to the first aspect of the present invention, there is provided a semiconductor device in which a nonvolatile memory cell with a floating gate electrode and a field effect transistor are formed on a semiconductor substrate, comprising
a first conductive layer which is formed on the semiconductor substrate via a tunnel insulating film, and patterned into a predetermined shape,
a first interlevel insulating film which is formed on the semiconductor substrate so as to cover the field effect transistor, and has a first opening for exposing a surface of the first conductive layer,
a second conductive layer which is formed on the first conductive layer inside the first opening, and patterned into a predetermined shape, and
a control gate electrode of the nonvolatile memory cell which is formed on the second conductive layer via an internal insulating film patterned into a predetermined shape,
wherein the first and second conductive layers constitute the floating gate electrode, and the first conductive layer has a planar shape which can be formed at the same time as a gate electrode of the field effect transistor.
In the semiconductor device according to the first aspect, the floating gate electrode of the nonvolatile memory cell is constituted by the first conductive layer formed on the semiconductor substrate via the tunnel insulating film, and the second conductive layer formed on the first conductive layer inside the first opening of the first interlevel insulating film. The first conductive layer has a planar shape which can be formed at the same time as the gate electrode of the field effect transistor.
For this reason, the first conductive layer and the gate electrode of the field effect transistor can be simultaneously formed. In addition, the second conductive layer, internal insulating film, and control gate electrode unique to the nonvolatile memory cell can be formed after the first interlevel insulating film covers the field effect transistor. Therefore, the manufacturing process concerning formation of the field effect transistor need hardly be changed. The manufacturing process and the manufacturing equipment can be easily shared, and sharing realizes low manufacturing cost.
Since the second conductive layer is formed inside the first opening, the planar shape of the second conductive layer can be widened without changing the occupied area of the nonvolatile memory cell. By widening the planar shape of the second conductive layer, the overlapping area between the floating and control gate electrodes increases to increase the electrostatic capacitance between the floating and control gate electrodes. Thus, the capacitive coupling ratio increases to realize driving by low voltage.
To form the first conductive layer at the same time as the gate electrode of the field effect transistor, the first conductive layer suffices to have a planar shape which can be patterned at the same time as the gate electrode of the field effect transistor. For example, the width of the planar shape of the first conductive layer is set almost equal to the gate length of the field effect transistor.
According to the second preferable aspect of the semiconductor device of the present invention, the planar shape of the first conductive layer is substantially the same as a planar shape of the gate electrode. This facilitates simultaneous formation of the first conductive layer and the gate electrode of the field effect transistor.
According to the third preferable aspect of the semiconductor device of the present invention, the semiconductor device further comprises an interconnection layer electrically connected to a source/drain region of the field effect transistor via a contact hole formed in the first interlevel insulating film, and the control gate electrode is made of the same material as the interconnection layer. Since the control gate electrode and the interconnection layer can be simultaneously formed, the manufacturing process can be simplified to reduce the manufacturing cost.
According to the fourth preferable aspect of the semiconductor device of the present invention, the semiconductor device further comprises a second interlevel insulating film which has a trench communicating with the contact hole and is formed on the first interlevel insulating film, the second interlevel insulating film has a second opening for exposing the internal insulating film, the control gate electrode is buried in the second opening, and the interconnection layer is buried in the trench. In this case, the interconnection layer is formed as a so-called buried interconnection, which is advantageous to high integration degree and high density.
According to the fifth preferable aspect of the present invention, the second conductive layer extends onto the second interlevel insulating film outside the first opening together with the internal insulating film. In this case, the electrostatic capacitance between the floating and control gate electrodes can be further increased.
According to the sixth preferable aspect of the present invention, the internal insulating film and the second conductive layer are patterned into substantially the same shape. Since the second conductive layer and the internal insulating film can be simultaneously patterned, the manufacturing process can be further simplified to reduce the manufacturing cost.
To achieve the third object, according to the seventh aspect of the present invention, there is provided a method of manufacturing a semiconductor device in which a nonvolatile memory cell with a floating gate electrode and a field effect transistor are formed on a semiconductor substrate, comprising
the first step of forming the field effect transistor, and a first conductive layer patterned into a predetermined shape via a tunnel insulating film on the semiconductor substrate,
the second step of forming a first interlevel insulating film on the semiconductor substrate so as to cover the first conductive layer and the field effect transistor,
the third step of selectively etching the first interlevel insulating film to form a first opening for exposing a surface of the first conductive layer,
the fourth step of forming a structure made up of a second conductive layer which is formed on the first conductive layer inside the first opening and patterned into a predetermined shape, and an internal insulating film which is formed on the second conductive layer and patterned into a predetermined shape, and
the fifth step of forming a control gate electrode of the nonvolatile memory cell on the internal insulating film,
wherein the first and second conductive layers constitute the floating gate electrode, and the first conductive layer has a planar shape which can be formed at the same time as a gate electrode of the field effect transistor.
According to the semiconductor device manufacturing method of the present invention, the manufacturing process and the manufacturing equipment can be easily shared for substantially the same reason as described in the semiconductor device of the present invention. Sharing can reduce the manufacturing cost. Moreover, driving by low voltage is realized.
According to the eighth preferable aspect of the semiconductor device manufacturing method of the present invention, the planar shape of the first conductive layer is substantially the same as a planar shape of the gate electrode. This enables simultaneously forming the first conductive layer and the gate electrode of the field effect transistor.
According to the ninth preferable aspect of the semiconductor device manufacturing method of the present invention, the fifth step comprises forming, at the same time as the control gate electrode, an interconnection layer electrically connected to a source/drain region of the field effect transistor via a contact hole formed in the first interlevel insulating film. The manufacturing process can be simplified to reduce the manufacturing cost.
According to the 10th preferable aspect of the semiconductor device manufacturing method of the present invention, the method further comprises the sixth step of forming on the first interlevel insulating film a second interlevel insulating film having a second opening for exposing the internal insulating film and a trench communicating with the contact hole, and the fifth step comprises burying the control gate electrode in the second opening and burying the interconnection layer in the trench. The interconnection layer is formed as a so-called buried interconnection, which is advantageous to high integration degree and high density.
According to the 11th preferable aspect of the semiconductor device manufacturing method of the present invention, the second conductive layer extends onto the second interlevel insulating film outside the first opening together with the internal insulating film. This can further increase the electrostatic capacitance between the floating and control gate electrodes.
According to the 12th preferable aspect of the semiconductor device manufacturing method of the present invention, the internal insulating film and the second conductive layer are patterned into substantially the same shape. Since the second conductive layer and the internal insulating film can be simultaneously patterned, the manufacturing process can be further simplified to reduce the manufacturing cost.
The semiconductor device and manufacturing method of the present invention in the above aspects are preferably applied to a semiconductor device in which a field effect transistor is formed in a logic circuit region on a semiconductor substrate.
The above and many other objects, features and advantages of the present invention will become manifest to those skilled in the art upon making reference to the following detailed description and accompanying drawings in which preferred embodiments incorporating the principle of the present invention are shown by way of illustrative examples.